Open AccessMeta‐stability immunity technique for high speed SAR ADCs
Author(s) -
Qiu L.,
Tang K.,
Zheng Y.J.,
Siek L.
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.4001
Subject(s) - effective number of bits , successive approximation adc , cmos , overhead (engineering) , electronic engineering , chip , power consumption , power (physics) , noise immunity , bit (key) , stability (learning theory) , computer science , engineering , electrical engineering , capacitor , voltage , electronic circuit , physics , computer security , quantum mechanics , machine learning
An 8‐bit 4 GS/s 8‐channel time‐interleaved successive approximation register (SAR) analogue‐to‐digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta‐stability immunity technique is proposed, which utilises pre‐installation to eliminate uncertain decision. The technique has negligible design overhead in terms of power and silicon area. The ADC chip was fabricated in a 65 nm CMOS technology. It achieves an ENOB of 7.45 bits, with 48 mW power consumption and an area of 0.075 mm 2 .