Open AccessSelf‐adjusting sensing circuit without speed penalty for reliable STT‐MRAM
Author(s) -
Ryu J.W.,
Kwon K.W.
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.3877
Subject(s) - magnetoresistive random access memory , computer science , electronic engineering , electrical engineering , engineering , random access memory , computer hardware
A self‐adjusting sensing circuit spin‐torque transfer magnetic random access memory (STT‐MRAM) is proposed. STT‐MRAM is considered to be the most promising candidate among the new emerging memories. However, read performance has emerged as a new bottleneck, because of its low tunnelling magneto‐resistance ratio (TMR) and low read current. The proposed self‐adjusting sensing circuit shows an improved sensing margin, overcoming the weaknesses of the STT‐MRAM. The proposed circuit using Verilog‐A model, a 65 nm complementary metal–oxide–semiconductor process also evaluated, and Monte Carlo analysis. The results of analysis show that the proposed circuit ensures a certain sensing margin, which is more than 200 mV in TMR 150% and about 50 mV in TMR 100%.