Low‐cost multi‐standard video transform core using time‐distribution scheme

Cost‐effective two‐dimensional (2D) discrete cosine transform (DCT) and inverse DCT architectures capable of supporting multiple standards of MPEG, H.264 and VC‐1 are presented. The proposed core utilises a 1D core and a transposed memory to achieve a low cost design. Multi‐level factor share is implemented in conjunction with distributed arithmetic in a system to enable the sharing of the coefficient matrix circuit in order to reduce hardware costs. The proposed approach employs a time‐distribution scheme to enable the simultaneous processing of the first and second dimensions to enhance throughput. A high efficiency of this approach was verified by fabricating a test chip using the TSMC 0.18 μm CMOS process. The architecture has an operating frequency of 200 MHz, and throughput of 800 M‐pixels/s with a gate count of 44.5 K.