Open AccessUltra‐low power pass‐transistor‐logic‐based delay line design for sub‐threshold applications
Author(s) -
Tadros R.N.,
Dasari N.,
Beerel P.A.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.3240
Subject(s) - transistor , electronic engineering , threshold voltage , logic gate , pass transistor logic , computer science , linearity , monte carlo method , power (physics) , circuit design , ultra low power , leakage power , energy (signal processing) , logic synthesis , leakage (economics) , voltage , electrical engineering , engineering , physics , mathematics , statistics , quantum mechanics , power consumption , economics , macroeconomics
Designs that operate at sub‐threshold voltages are a promising response to the ultra‐low power demands of many modern applications with relaxed performance requirements. Towards this approach, a pass‐transistor‐logic‐based programmable delay line (DL) circuit is presented that is designed specifically for sub‐threshold operation. Compared with the commonly used design, the DL consumes 79.2% less dynamic energy, 83.5% less leakage power, 47.2% better linearity across codewords, 58.6% smaller active area, and with similar resiliency to variations across Monte Carlo simulations.