Open AccessVoltage‐in‐current formulation for the latency insertion method for improved stability
Author(s) -
Tan K.H.,
Goh P.,
Ain M.F.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.3223
Subject(s) - latency (audio) , voltage , transient (computer programming) , transient analysis , insertion loss , control theory (sociology) , stability (learning theory) , time domain , computer science , electronic engineering , transient response , topology (electrical circuits) , engineering , electrical engineering , telecommunications , control (management) , artificial intelligence , machine learning , computer vision , operating system
A new formulation for the latency insertion method (LIM) by implicitly substituting the voltages in the currents is presented. LIM is a fast transient analysis technique for large networks. However, due to its explicit formulation, it has a limitation on the time step size to guarantee numerical stability, similar to the finite‐difference time‐domain technique. This limits the efficiency of the method particularly where small parasitic inductances and capacitances are present which necessitates the use of very small time steps. Using the new formulation, an improved LIM is presented, where accurate and stable results can be obtained without limitation on the time step size.