Open AccessHarmonic‐free and low cost delay‐locked loop with a 20–80% input duty cycle
Author(s) -
Wei Xing,
Chen Zhujia,
Li Wei,
Yang Haigang
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2016.3032
Subject(s) - duty cycle , delay locked loop , harmonic , cmos , control theory (sociology) , electronic engineering , controller (irrigation) , phase locked loop , computer science , electrical engineering , physics , voltage , engineering , jitter , acoustics , control (management) , agronomy , artificial intelligence , biology
A low‐cost two‐step delay locked loop (DLL) with a 20–80% input duty cycle is presented. For eliminating harmonic and zero‐trap locking issues along the whole range of digital controlled delay line, a hierarchy phase detector (HPD) is proposed to compare the phase difference between input reference clock and two phase‐isotonic clocks generated by sharing a common delay line. By monitoring of HPD's output, state controller can solve harmonic and zero‐trap locking issues while being naturally immune to the wide range of input duty cycle. With an asymmetric edge combiner, high duty cycle correction accuracy can be achieved. The proposed DLL is implemented in 55 nm CMOS technology with a 0.00574 mm 2 chip area. Simulation results show that the operation range of the proposed DLL is 0.3–1.6 GHz without the occurrence of harmonic and zero‐trap locking, and the range of input duty cycle is 20–80%. The power consumption is 0.76 mW at 1.6 GHz.