Open AccessDigital LDO with 1‐bit ΔΣ modulation for low‐voltage clock generation systems
Author(s) -
Song Haixin,
Rhee Woogeun,
Shim Inbo,
Wang Zhihua
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.2982
Subject(s) - low dropout regulator , cmos , electronic engineering , delay locked loop , modulation (music) , dropout voltage , ranging , voltage , computer science , voltage regulator , low voltage , dual loop , loop (graph theory) , phase locked loop , phase noise , electrical engineering , engineering , physics , mathematics , telecommunications , acoustics , combinatorics
A coarse‐fine dual‐loop digital low dropout regulator (DLDO) having a binary weighed transistor array in the coarse loop and a 1‐bit ΔΣ modulator in the fine loop is proposed. Compared with the conventional DLDO, the proposed architecture significantly reduces hardware complexity and alleviates matching requirement, enabling a robust DLDO design for low‐voltage phase‐locked loops. The proposed DLDO designed in 65 nm CMOS generates a noise‐shaped output voltage whose peak value is <1 mV with the load current ranging from 100 μA to 6 mA.