Open AccessHalf baud‐rate, low BER PAM‐4 CDR based on SS‐MMSE algorithm
Author(s) -
Liu Peng,
Guo Jun,
Jiang Yingtao
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.2944
Subject(s) - baud , algorithm , computer science , electronic engineering , mathematics , telecommunications , engineering , transmission (telecommunications)
A hardware‐efficient four‐level pulse amplitude modulation (PAM‐4) clock and data recovery (CDR) circuit for high speed serial links is proposed, following a sign‐sign minimum mean square error (SS‐MMSE) algorithm. Using a specially designed continuous‐sampling slope detector and a dual‐stage digital filter, the proposed SS‐MMSE CDR can align the clock phase well with the maximum vertical eye opening, as opposed to the conventional Bang‐Bang CDR which only finds the midpoint of a symbol, yet requiring extra clock phases or running at higher frequency. Simulation results confirm superior performance and implementation efficiency of this proposed SS‐MMSE PAM‐4 CDR over the Bang‐Bang design.