Open AccessTwo‐step injection clock generation technique for fractional‐ N MDLL
Author(s) -
Jee D.W.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2016.2755
Subject(s) - cmos , resolution (logic) , cpu multiplier , electronic engineering , process (computing) , power consumption , power (physics) , computer science , physics , clock skew , clock signal , engineering , jitter , quantum mechanics , artificial intelligence , operating system
Two‐step injection clock generation technique is presented for fine resolution fractional‐ N multiplying delay‐locked loop (MDLL). The coarse DLL generates multiple coarse clock phases, and then fine DLL performs fine phase control for MDLL injection clock. The proposed technique is applied to fractional‐ N MDLL and efficiently achieves 8b fractional frequency resolution. The MDLL designed in a 0.18 μm CMOS process occupies 0.065 mm 2 and generates 10 MHz frequency with 61 μW power consumption.