Open AccessConvenient method of digital PI‐CDR lock‐detection for phase noise elimination and enhanced jitter tolerance
Author(s) -
Li Tianyi,
Xu Xiaodong,
Yin Tao,
Li Wei,
Yang Haigang
Publication year - 2017
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.2699
Subject(s) - jitter , lock (firearm) , phase detector , phase locked loop , cmos , computer science , noise (video) , detector , electronic engineering , phase noise , electrical engineering , engineering , telecommunications , mechanical engineering , voltage , artificial intelligence , image (mathematics)
A lock‐detector for the digital phase interpolator based clock and dada recovery circuit (PI‐CDR) is proposed. The simple method could commendably lock the PI‐control code when the CDR is locked, which eliminates the systematic phase noise of the recovered clock without reducing the jitter tolerance ability. The proposed architecture is implemented in 0.13 μm CMOS and occupies area of 0.18 mm 2 .