Open AccessUnderestimation of measured self‐heating in nanowires by using gate resistance technique
Author(s) -
Mariniello G.,
Cassé M.,
Reimbold G.,
Pavanello M.A.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2016.2570
Subject(s) - materials science , optoelectronics , channel (broadcasting) , nanowire , thermal resistance , temperature measurement , dissipation , silicon nanowires , fin , silicon on insulator , gate oxide , silicon , thermal , electrical engineering , transistor , composite material , voltage , engineering , physics , quantum mechanics , meteorology , thermodynamics
The channel temperature rise is demonstrated due to self‐heating in narrow tri‐gate fully depleted silicon‐on‐insulator devices becomes inaccurate when extracted using the gate resistance thermometry. Thermal resistance and channel temperature have been extracted by both gate resistance measurements and 3D TCAD electrothermal simulations for tri‐gate wide and nanowire MOSFETs down to 12.5 nm fin width. A critical fin width around 500 nm the extracted channel temperature accessed by the gate resistance thermometry differs significantly from the actual channel temperature due to heat dissipation through the gate contacts is shown below, leading to significantly underestimated values.