Open AccessDithering‐based calibration of capacitor mismatch in SAR ADCs
Author(s) -
Wu Jianhui,
Wu Aidong,
Du Yuan
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2016.2551
Subject(s) - dither , capacitor , converters , calibration , electronic engineering , shaping , computer science , signal (programming language) , matching (statistics) , comparator , successive approximation adc , electronic circuit , switched capacitor , window (computing) , voltage , engineering , mathematics , electrical engineering , noise shaping , statistics , programming language , operating system
A novel dithering‐based calibration technique to correct capacitor mismatch in digital‐to‐analogue converter (DAC) used in successive approximation register analogue‐to‐digital converters is proposed. With dithering, weights of most significant bit capacitors can be measured accurately, which relaxes matching requirement in capacitive DAC. In addition, the bypass window technique is used to detect whether the output voltage of the DAC is within a predefined small window, which determines whether to inject the dithering signal. As a result, the proposed calibration can operate in the background. According to the simulation, the proposed calibration technique significantly improves capacitor matching without resorting to extensive computation or dedicated circuits.