2 × VDD output buffer with 36.4% slew rate improvement using leakage current compensation | Zendy

Wang C.C. | Zendy; Tsai T.Y. | Zendy; Lee T.J. | Zendy; Ruan K.W. | Zendy

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2 × VDD output buffer with 36.4% slew rate improvement using leakage current compensation

Author(s) -

Wang C.C.,

Tsai T.Y.,

Lee T.J.,

Ruan K.W.

Publication year - 2017

Publication title -

electronics letters

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.375

H-Index - 146

ISSN - 1350-911X

DOI - 10.1049/el.2016.2351

Subject(s) - slew rate , leakage (economics) , cmos , compensation (psychology) , materials science , reliability (semiconductor) , electrical engineering , electronic engineering , degradation (telecommunications) , buffer (optical fiber) , optoelectronics , engineering , physics , voltage , power (physics) , psychology , quantum mechanics , psychoanalysis , economics , macroeconomics

A 2 × VDD output buffer using leakage current compensation is demonstrated. With the proposed leakage current compensation circuit, the SR (slew rate) is improved 36.4–101.89% based on on‐silicon measurement results given different VDDIO (1.0/1.2/1.8 V) and temperatures (from 0 to 100°C). The data rate is 510/630/400 MHz for VDDIO at 1.8/1.2/1.0 V, respectively. Moreover, the reliability problem, the gate oxide overstress and the hot carrier degradation is avoided. The proposed design is implemented using a typical 90 nm CMOS process. The active area is 0.425 × 0.0563 mm. The SR is measured in the range from 0.766 to 2.585 V/ns.

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