Open AccessESD protection design and enhancement in the power 60‐V n‐channel LDMOS by embedded‐SCR anode islands
Author(s) -
Chen S.L.,
Chen K.J.,
Chen H.W.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.2232
Subject(s) - ldmos , electrostatic discharge , anode , materials science , transistor , robustness (evolution) , high voltage , electrical engineering , thyristor , cmos , optoelectronics , power semiconductor device , voltage , reliability (semiconductor) , power (physics) , engineering , electrode , chemistry , physics , biochemistry , quantum mechanics , gene
An electrostatic discharge (ESD) strengthening design of high‐voltage (HV) n ‐channel laterally diffused metal–oxide semiconductor (nLDMOS) transistors combined with embedded‐SCR anode islands is investigated. After a systematic layout implementation and analysis, the anti‐ESD robustness [or secondary breakdown current ( I t2 )] of drain pnp ‐arranged and SCR isolated‐type DUTs were higher than 7‐A (ESD reliability improvements of these nLDMOS‐SCR devices were more than 282.5% (199.2%) higher than that of the pure nLDMOS ( pnp ‐stripe) component. Also, it can be found that the ESD robustness of the pnp ‐arranged type is greater than the npn ‐arrangement. Therefore, an adequate architecture of an HV nLDMOS device embedded with an SCR ( pnp ‐arranged) and SCR isolated manner can gain high ESD‐reliability immunity.