Open AccessFractional spur reduction technique using 45° phase dithering in phase interpolator based all‐digital phase‐locked loop
Author(s) -
Ko J.,
Heo M.,
Lee J.,
Kim C.,
Lee M.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2016.2098
Subject(s) - dither , spur , offset (computer science) , phase locked loop , reduction (mathematics) , phase (matter) , loop (graph theory) , optics , mathematics , computer science , electronic engineering , physics , phase noise , bandwidth (computing) , telecommunications , engineering , geometry , structural engineering , quantum mechanics , combinatorics , programming language
A spur reduction technique in fractional‐N phase‐locked loops based on a current‐mode phase interpolator (CMPI) is presented by dithering input signals of the CMPI. CMPI shows deterministic phase error having symmetrical profile around 45° offset in each quadrant, and this non‐linear property leads to fractional spurs. The proposed 45° phase rotator with digital compensation reduces the fractional spur by 18.57 dB at most, and average improvement of fractional tones is 7.89 dB in 2 MHz frequency step measurement.