Open Access5.3 GHz 42% PAE class‐E power amplifier with 532 mW/mm 2 power area density in 180 nm CMOS process
Author(s) -
Alsuraisry H.,
Wu M.H.,
Huang P.S.,
Tsai J.H.,
Huang T.W.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2016.1629
Subject(s) - inductor , cmos , amplifier , electrical engineering , choke , power added efficiency , cascode , materials science , capacitor , inductance , power density , power (physics) , rf power amplifier , optoelectronics , engineering , physics , voltage , quantum mechanics
A 5.3 GHz high‐efficiency and low‐cost class‐E power amplifier (PA) implemented in a 180 nm CMOS process is presented. Cascode configuration is utilised in the class‐E PA to achieve high efficiency due to its high gain property and low drain‐to‐source parasitic capacitor. Through the trade‐off between inductance and inductor loss, an optimised RF choke inductor for fully integrated class‐E PA design can be selected to achieve high efficiency while maintaining compact circuit size. The class‐E CMOS PA demonstrates the highest Power Added Efficiency (PAE) of 42% and greatest power area density of 532 mW/mm 2 in 0.263 mm 2 chip area to date.