Open AccessAbstraction techniques to improve scalability of equivalence verification for NCL circuits
Author(s) -
Wijayasekara V.M.,
Rollie A.T.,
Hodges R.G.,
Srinivasan S.K.,
Smith S.C.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.1138
Subject(s) - computer science , scalability , abstraction , asynchronous communication , electronic circuit , formal equivalence checking , computer architecture , equivalence (formal languages) , asynchronous circuit , computer engineering , formal verification , programming language , mathematics , engineering , electrical engineering , operating system , computer network , clock signal , synchronous circuit , philosophy , epistemology , discrete mathematics
Asynchronous NULL convention logic (NCL) circuits are dual‐rail quasi‐delay‐insensitive circuits that have many applications in high radiation and extreme temperature fluctuation environments such as space exploration. Two abstraction techniques are proposed that can be used to drastically improve the efficiency and scalability of formal equivalence verification targeted at NCL circuits. The effectiveness of the abstraction techniques have been demonstrated using a number of multiply and accumulate circuit benchmarks.