Open Access19.1 GHz 18 mW divide‐by‐3 heterodyne injection locking frequency divider in 0.18 µm CMOS technology
Author(s) -
Huang JianHua,
Yu XiaoPeng,
Xu ShiYi,
Jin Jing,
Yu FaXin
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2016.0962
Subject(s) - frequency divider , injection locking , cmos , heterodyne (poetry) , electrical engineering , frequency multiplier , superheterodyne receiver , electronic engineering , inductor , voltage , current divider , resistive touchscreen , engineering , materials science , physics , radio frequency , optics , acoustics , laser
A divide‐by‐3 frequency divider based on heterodyne injection‐locking technique is presented. An injection‐locking LC oscillator with resistive feedback and differential signal injection is implemented to achieve higher injection efficiency over a wider range. Moreover, by optimisation of inter‐stage loading as well as filter‐less design, only one inductor is used in this design to save silicon area. Implemented in a standard 0.18 µm CMOS process, the proposed divide‐by‐3 divider has a locking range from 17 to 19.1 GHz without extra frequency tuning and consumes 10 mA from a 1.8 V supply voltage.