Open AccessContinuous‐time ΔΣ modulator having time‐interleaved switched‐capacitor brief‐return‐to‐zero DAC with first‐order jitter noise shaping
Author(s) -
Choi M.Y.,
Roh H.D.,
Lee M.J.,
Kwon S.,
Lee Y.H.,
Park H.J.,
Kong B.S.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.0960
Subject(s) - jitter , switched capacitor , delta sigma modulation , bandwidth (computing) , electronic engineering , intersymbol interference , noise (video) , capacitor , computer science , electrical engineering , telecommunications , engineering , voltage , channel (broadcasting) , artificial intelligence , image (mathematics)
A continuous‐time delta‐sigma modulator (CT DSM) having a time‐interleaved switched‐capacitor brief‐return‐to‐zero DAC with first‐order jitter noise shaping is proposed to reduce the sensitivity to clock jitter. The proposed CT DSM allows higher power efficiency and lower intersymbol interference by using a time‐interleaved nearly full clock period integration with its current returning to zero briefly. Evaluation results indicate that the proposed third‐order single‐bit CT DSM operating at 168‐MHz achieves 79.1 dB SNDR with 50% reduced DAC current for a 2‐MHz signal bandwidth having 1% clock jitter as compared with conventional techniques.