Open AccessSRAM cell with asymmetric pass‐gate nMOSFETs for embedded memory applications
Author(s) -
He Weiwei,
Chen Jing,
Luo Jiexin,
Chai Zhan,
Wang Xi
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.0938
Subject(s) - static random access memory , transistor , memory cell , cmos , materials science , node (physics) , silicon on insulator , mosfet , optoelectronics , planar , leakage (economics) , logic gate , electronic engineering , voltage , electrical engineering , computer science , silicon , engineering , computer graphics (images) , structural engineering , economics , macroeconomics
A novel asymmetric static RAM (SRAM) cell is fabricated on planar silicon‐on‐insulator CMOS technology, in which pass‐gate (PG) transistors are asymmetric. Since lightly doped drain structure of PG transistors use only gate‐to‐source, this cell improves read stability by 43% when compared with the conventional SRAM 6T symmetric cell. Additionally, cell‐leakage current reduces by 24% also due to the PG transistor gate‐to‐drain underlap design. Although it needs more current to write data to storage node, but no more voltage is needed based on measurements. The novel cell is still suitable for embedded memory.