Open AccessFractional‐ N PLL with multi‐element fractional divider for noise reduction
Author(s) -
Sanyal Arindam,
Yu Xueyi,
Zhang Yanlong,
Sun Nan
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2016.0680
Subject(s) - phase locked loop , frequency divider , phase noise , noise (video) , pll multibit , noise reduction , electronic engineering , reduction (mathematics) , mathematics , control theory (sociology) , physics , computer science , engineering , acoustics , cmos , control (management) , artificial intelligence , image (mathematics) , geometry
A novel technique to suppress quantisation noise in a ΔΣ fractional‐ N phase‐locked loop (PLL) using a fine‐resolution multi‐element fractional divider is presented. The proposed technique suppresses noise uniformly over the entire frequency range. It is mostly digital and is applicable for both analogue and digital PLLs. The proposed technique with an eight‐element fractional divider can suppress the quantisation noise by 18 dB compared with a conventional fractional‐ N PLL.