4.2 GHz 0.81 mW triple‐modulus prescaler based on true single‐phase clock

A dual‐modulus prescaler based on true single‐phase clock D flip‐flop is presented. Instead of using the conventional digital logic circuit, the pass transistor logic circuit is applied to reduce the number of the transistors and the power of the divider. By adding only two additional transistors, a dual‐modulus operation is achieved. Implemented in a standard 180 nm CMOS process, the proposed divide‐by 6/7/8 prescaler based on the proposed dual‐modulus one achieves an operating frequency of 4.2 GHz with a measured power consumption of 0.81 mW for a 1.2 V supply.