Open AccessEnergy‐efficient switching method for SAR ADCs with bottom plate sampling
Author(s) -
Zhang Yulin,
Bonizzoni Edoardo,
Maloberti Franco
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2016.0289
Subject(s) - converters , successive approximation adc , energy (signal processing) , capacitor , reduction (mathematics) , sampling (signal processing) , electronic engineering , shaping , computer science , scheme (mathematics) , mathematics , engineering , electrical engineering , voltage , telecommunications , statistics , mathematical analysis , geometry , detector
A high energy‐efficiency capacitor switching scheme for successive approximation register (SAR) analogue‐to‐digital converters (ADCs) is presented. The switching method, verified on a 10‐bit SAR scheme that uses bottom plate sampling, achieves an average switching energy and area reduction of 99.32 and 96.5%, respectively, with respect to the conventional solution.