Open AccessMiller effect suppression of tunnel field‐effect transistors (TFETs) using capacitor neutralisation
Author(s) -
Choi W.Y.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2016.0225
Subject(s) - capacitor , transistor , materials science , electrical engineering , field effect transistor , voltage , tunnel field effect transistor , miller , optoelectronics , logic gate , electronic engineering , computer science , engineering , ecology , biology
A novel method of suppressing the Miller effects of tunnel field‐effect transistors (TFETs) is proposed by using capacitor neutralisation. Since TFETs suffer from more severe Miller effects than metal‐oxide‐semiconductor FETs, conventional ways such as short‐gate structures are not sufficient to fully suppress the Miller effects of TFETs. For further reduction of Miller effects, capacitor neutralisation is applied to TFET circuit design for the first time. An exemplary circuit has been shown to confirm the effectiveness of capacitor neutralisation such as differential cascade voltage switch logic. The suppression of Miller effects has been discussed in terms of undershoot, switching delay, power consumption and circuit area.