Open AccessDesign of reversible circuits with high testability
Author(s) -
Gaur H.M.,
Singh A.K.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.0161
Subject(s) - testability , electronic circuit , benchmark (surveying) , computer science , design for testing , set (abstract data type) , logic synthesis , reduction (mathematics) , electronic engineering , logic gate , algorithm , mathematics , reliability engineering , engineering , electrical engineering , geometry , geodesy , programming language , geography
A new method of designing reversible logic circuits which can be adopted by any synthesis technique to produce parity preserving reversible circuits based on Multiple Controlled Tofolli gates is proposed. The designed circuit using proposed methodology is easily testable by checking the input and output parity. A set of benchmark circuits and corresponding testable designs are implemented. The results under testable designs show an average reduction of 32% in operating cost as compared to prior work.