Open AccessUltra low overhead error mask flip‐flop in near threshold voltage processor design
Author(s) -
Hao Ziyi,
Xiang Xiaoyan,
Chen Chen,
Meng Jianyi,
Yan Xiaolang
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2016.0091
Subject(s) - flip flop , overhead (engineering) , computer science , error detection and correction , voltage , cmos , electronic engineering , transistor , margin (machine learning) , electrical engineering , engineering , algorithm , machine learning , operating system
Reducing circuit supply voltage to near‐threshold (NT) region is an effective technique for achieving better energy efficiency in current ultra‐low power circuit design. However, circuit variation problem becomes extremely worse in NT region and requires more design margin. Error detection and correction (EDAC) designs can remove circuit margin by solving transient error dynamically, but many of the traditional EDAC designs cause large area overhead and cycle per instruction (CPI) penalty. A compact timing error mask flip‐flop (EMFF) based on error masking with ultra‐low overhead by only adding six transistors (four for error detection and two for error correction) to the conventional flip‐flop with 0 CPI penalty is presented. The proposed EMFF reduces system area overhead significantly. Therefore, the timing error tolerance ability is expanded and higher energy efficiency can be archived. EMFF is realised in an industrial processor in SMIC 40 nm CMOS with only 6.8% area overhead, compared with the original processor. At 0.5 V, the EMFF system gains 18.6% performance increasing than the most compact previous work with 3% higher efficiency.