Open AccessLow‐power bottom‐plate sampling capacitor‐splitting DAC for SAR ADCs
Author(s) -
Yazdani B.,
Khorami A.,
Sharifkhani M.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.0087
Subject(s) - successive approximation adc , converters , capacitor , voltage , energy (signal processing) , electronic engineering , power (physics) , sampling (signal processing) , voltage reference , shaping , computer science , electrical engineering , engineering , mathematics , physics , filter (signal processing) , quantum mechanics , statistics
A highly energy‐efficient switching method for capacitor‐splitting digital‐to‐analogue converter (DAC) in successive approximation register (SAR) analogue‐to‐digital converters (ADCs) is presented. In the proposed DAC, a bottom‐plate sampling method is introduced which requires only one reference voltage ( V cm = 1/2 V ref ) during the entire DAC switching steps. Therefore, in addition to the switching energy reduction, the precision of the DAC is increased since only one reference voltage is used. The DAC average switching energy and the area are reduced by 98.44% and 50% compared with the conventional binary weighted DAC.