Open AccessHigh speed and reliability gearbox for 100GE physical coding sublayer
Author(s) -
Weihua Ruan,
Qingsheng Hu
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2016.0084
Subject(s) - reliability (semiconductor) , cmos , computer science , power consumption , coding (social sciences) , electronic engineering , power (physics) , engineering , mathematics , statistics , physics , quantum mechanics
Two differently structured 66:8 gearboxes according to the IEEE802.3ba standard for 100GE transmit (TX) physical coding sublayer (PCS) system are described. By comparing their number of cells (area), power consumption, speed and reliability, the better one is applied to the 100GE TX PCS circuit. The better one is based on a kind of register which uses a round‐robin saving way. It is this special deposit way that makes it possible to take out the output data within a certain range, so as to overcome the influence of the phase difference between the input and the output clock and greatly improve its speed and reliability. The synthesis result shows that this structure of the gearbox can make it possible to run reliably at more than 700 MHz clock frequency (using the 0.18 μm CMOS standard cells). The PCS circuit which includes the better gearbox has been taped out using the 0.18 μm CMOS process and the measured results show that it can run properly at a speed of 100 Gbit/s.