Open AccessFractional‐ N multiplying delay‐locked loop with delay‐locked loop‐based injection clock generation
Author(s) -
Jee D.W.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.4531
Subject(s) - jitter , delay locked loop , phase locked loop , frequency divider , loop (graph theory) , cmos , frequency synthesizer , electronic engineering , clock generator , frequency multiplier , delay line oscillator , computer science , control theory (sociology) , physics , clock signal , mathematics , engineering , control (management) , combinatorics , artificial intelligence
A fractional‐ N multiplying delay‐locked loop (MDLL) with delay‐locked loop (DLL)‐based injection clock generation is presented. By exploiting multiphase output of DLL which delay is locked to the period of output frequency, the proposed architecture performs a fractional clock multiplication with MDLL, while eliminating deterministic jitter from fractional divider. The proposed MDLL is designed in a 0.18 μm CMOS process and achieves 31.25 kHz frequency resolution with 1 MHz reference frequency. It occupies an active area of 0.055 mm 2 , and consumes 45 μW for 10 MHz frequency generation, showing energy efficiency figure‐of‐merit (FoM) of 4.5 μW/MHz.