Open AccessHigh‐performance single‐cycle memristive multifunction logic architecture
Author(s) -
Yang X.,
Adeyemo A.A.,
Jabir A.,
Mathew J.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.4394
Subject(s) - architecture , computer architecture , electronic engineering , logic gate , computer science , logic family , memristor , electrical engineering , logic synthesis , engineering , art , visual arts
A low‐complexity high‐performance memristive multifunction logic architecture is presented for low‐power high‐frequency operations in a single cycle, which does not require additional control input/logic and multicycle setup/operation. It can be seamlessly integrated with the existing CMOS technology with just one transistor and four memristors design and without additional overhead. This technique can realise both XOR/AND and XNOR/OR operations simultaneously. Experimental results show that this technique significantly outperforms both CMOS and existing hybrid memristor‐CMOS‐based designs in terms of chip area, power consumptions, and reliable performance especially at high frequencies. With the help of full‐adder designs, it is also demonstrated that the multifunctionality of this architecture can result in highly compact designs.