Open AccessDigital predistortion architecture with reduced ADC dynamic range
Author(s) -
Liu Ying,
Quan Xin,
Shao Shihai,
Tang Youxi
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2015.4174
Subject(s) - predistortion , dynamic range , amplifier , electronic engineering , successive approximation adc , computer science , linearity , signal (programming language) , analog to digital converter , radio frequency , high dynamic range , electrical engineering , engineering , telecommunications , bandwidth (computing) , comparator , voltage , programming language
A digital predistortion (DPD) architecture is proposed with the dynamic range of the feedback channel being reduced. In this architecture, an extra radio frequency (RF) chain is deployed to cancel the linear components of the power amplifier (PA) output signal to reduce the dynamic range requirement on the analogue‐to‐digital converter (ADC) of the feedback channel. Subsequently in digital domain, the original PA output signal is estimated from both the digital replica of the RF cancelling signal and the acquired residual signal after cancellation, which is utilised to extract the DPD coefficients. Experimental results validate the effectiveness and superior performances of the proposed architecture, particularly with the number of ADC bits being reduced.