Open Access9‐bit time–digital‐converter‐assisted compressive‐sensing analogue–digital‐converter with 4 GS/s equivalent speed
Author(s) -
Hu B.,
Ren F.,
Chen Z.Z.,
Jiang X.,
Chang M.C.F.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.3778
Subject(s) - comparator , successive approximation adc , cmos , electronic engineering , effective number of bits , 12 bit , voltage , analog to digital converter , nyquist rate , integrating adc , figure of merit , nyquist–shannon sampling theorem , computer science , electrical engineering , engineering , capacitor , sampling (signal processing) , ćuk converter , filter (signal processing) , computer vision
A novel 9‐bit time–digital‐converter (TDC)‐assisted analogue–digital‐converter (ADC) supporting energy‐efficient high‐speed compressive‐sensing (CS) operation is presented. With a voltage–time‐converter serving as the cross‐domain residue conveyer, the proposed two‐stage self‐timed pipeline ADC architecture hybrids a voltage‐domain comparator‐interleaved successive‐approximation (SAR) ADC front‐end and a time‐domain locally readjusted folding two‐dimensional Vernier TDC back‐end. Implemented in 65 nm CMOS technology, the prototype benefits from both the CS‐enabled sub‐Nyquist operation and the hybrid quantisation scheme, leading up to 4 GS/s equivalent speed with 34.2 dB signal‐noise‐distortion‐ratio (SNDR) and a figure‐of‐merit (FOM) of 101 fJ/conversion step.