Open AccessParallel in/out systolic AB 2 architecture with low complexity in GF (2 m )
Author(s) -
Choi S.H.,
Lee K.J.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.3681
Subject(s) - multiplier (economics) , systolic array , arithmetic , scheme (mathematics) , computational complexity theory , parallel computing , computer science , mathematics , architecture , algorithm , very large scale integration , embedded system , mathematical analysis , economics , macroeconomics , art , visual arts
Efficient GF (2 m ) arithmetic clearly affects the performance of compute‐intensive applications. A new low‐complexity parallel‐in/out systolic AB 2 multiplier based on the least significant bit‐first scheme is presented. Compared with related works, the scheme yields significantly lower area‐time complexity.