Open AccessCalibrating sample and hold stages with pruned Volterra kernels
Author(s) -
Centurelli F.,
Monsurrò P.,
Rosato F.,
Ruscio D.,
Trifiletti A.
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.3269
Subject(s) - linearity , robustness (evolution) , capacitor , nonlinear system , control theory (sociology) , sampling (signal processing) , amplifier , electronic engineering , sample and hold , mathematics , computer science , cmos , voltage , engineering , telecommunications , physics , electrical engineering , biochemistry , chemistry , control (management) , quantum mechanics , artificial intelligence , detector , gene
Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal‐to‐noise‐and‐distortion ratio (SNDR): CMOS switch non‐idealities, amplifier nonlinearity, and incomplete settling. It is possible to model and correct distortions using Volterra kernels, which can be rather resource‐consuming as the number of parameters to estimate rapid increases with the order and length of the kernels. In this reported work, it is shown that a switched capacitor SHA, simulated using the 45 nm process by STMicroelectronics, can be calibrated to achieve a 10–24 dB improvement in SNDR. Computational costs are kept low using a different lag value for each kernel, and iteratively pruning the elements of the Volterra kernels which affect linearity the least. A technique for estimation and out‐of‐sample validation is presented and robustness checks are performed. A performance gain of 8.5 dB can be achieved with as few as 17 correction parameters, while 21 coefficients are enough to gain 12.2 dB, and 36 to gain 18.4 dB.