Open AccessHigh‐performance, low‐cost, and highly reliable radiation hardened latch design
Author(s) -
Yan Aibin,
Liang Huaguo,
Huang Zhengfeng,
Jiang Cuiyun
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2015.3020
Subject(s) - cmos , upset , soft error , single event upset , charge sharing , dissipation , electronic engineering , computer science , propagation delay , power (physics) , radiation hardening , transistor , electrical engineering , engineering , static random access memory , voltage , physics , mechanical engineering , quantum mechanics , detector , thermodynamics
Technology scaling results in that, soft errors, due to radiation‐induced single event double‐upset (SEDU) that affects double nodes through charge sharing, become a prominent concern in nanoscale CMOS technology. Existing hardened schemes suffer from being not fully SEDU‐immune, or perform with too large cost penalties regarding propagation delay, silicon area, and power dissipation. A novel high‐performance, low‐cost, and fully SEDU‐immune latch, referred to as HSMUF, is presented to tolerate SEDU when any arbitrary combination pair of nodes is affected by a particle striking. The latch mainly consists of a clock gating‐based triple path DICE and a multiple‐input Muller C‐element. Simulation results demonstrate the SEDU‐immunity and a 99.73% area–power–delay product saving for the HSMUF latch, compared with the SEDU fully immune DNCS‐SEUT latch.