Open AccessSimple high‐resolution CMOS phase frequency detector
Author(s) -
Suraparaju E.R.,
Arja P.V.R.,
Ren S.
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2015.2992
Subject(s) - jitter , phase frequency detector , phase locked loop , cmos , reset (finance) , electronic engineering , detector , signal edge , phase detector , capacitive sensing , phase (matter) , signal (programming language) , power (physics) , electrical engineering , computer science , engineering , capacitor , physics , voltage , digital signal processing , charge pump , quantum mechanics , analog signal , financial economics , economics , programming language
A high‐resolution phase frequency detector (PFD) is designed for high‐frequency signal detection and low jitter phase locked loop applications. The proposed PFD eliminates the reset path delay and usage of any latches, minimise the dead zone to near zero by generating narrow pulses at each input rising edge. In addition, the designed PFD completely removes unwanted output glitches, accepts inputs with a large difference in frequency, and also has the ability to drive a large capacitive load with minimal impact on performance. The proposed PFD is designed in 90 nm CMOS technology with a 1.2 V power supply. Simulation results indicate that the proposed design can operate over a wide range of frequencies from 10 kHz to 6 GHz and can detect phase differences for inputs as small as 125 fs for all frequencies of operation and for all process corners. The simulated power consumption is 75 µW at 166.6 MHz with an input phase difference of 125 fs.