Open AccessNear‐threshold all‐digital PLL with dynamic voltage scaling power management
Author(s) -
Chang C.W.,
Chang K.Y.,
Chu Y.H.,
Jou S.J.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.2672
Subject(s) - phase locked loop , jitter , frequency scaling , power (physics) , voltage , digitally controlled oscillator , time to digital converter , electronic engineering , power consumption , lock (firearm) , frequency deviation , voltage controlled oscillator , pll multibit , computer science , electrical engineering , control theory (sociology) , automatic frequency control , physics , engineering , clock signal , delay line oscillator , quantum mechanics , mechanical engineering , control (management) , artificial intelligence
A near‐threshold all‐digital phase‐locked loop (ADPLL) with a power management unit (PMU) is presented to make the proposed ADPLL work reliably across variations and power consumption as well is reduced. When operated under near‐threshold condition from 0.52 to 0.58 V V DD , the gated digitally controlled oscillator frequency range is from 90.8 to 245.7 MHz. When the ADPLL is operated at 0.52 V V DD , a lock‐in time of 9.5 μs at 100 MHz output clock frequency is measured with an rms period jitter of 0.17% UI. With the PMU, the ADPLL power reduction at 130 MHz output frequency is 39% and the buck converter power consumption is nearly 30 μW. Consequently, the proposed ADPLL with PMU is suitable to event‐driven or low‐voltage applications.