Open Access2 ps resolution, fine‐grained delay element in 28 nm FDSOI
Author(s) -
Hua W.,
Tadros R.N.,
Beerel P.
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.2667
Subject(s) - biasing , silicon on insulator , optoelectronics , electronic engineering , silicon , voltage , materials science , computer science , physics , electrical engineering , engineering
A novel diversely body‐biased current‐starved delay element (DE) architecture for fine‐grained DEs is presented. Using fully depleted silicon‐on‐insulator back‐body biasing, it achieves a resolution of 2 ps with a delay quantisation error of 7.1%. Compared with the state‐of‐the‐art DEs, it exhibits the least leakage current and efficient overall energy consumption and is the most robust to process variations.