Open AccessDesign guidelines of tunnelling field‐effect transistors for the suppression of work‐function variation
Author(s) -
Choi W.Y.
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.2625
Subject(s) - quantum tunnelling , grain size , materials science , transistor , field effect transistor , optoelectronics , work function , semiconductor , work (physics) , metal , reduction (mathematics) , electrical engineering , engineering , metallurgy , mechanical engineering , mathematics , voltage , geometry
Design guidelines to suppress the work‐function variation (WFV) effects of tunnelling field‐effect transistors (TFETs) have been discussed in comparison with metal–oxide–semiconductor FETs for the first time. The effects of metal‐gate materials and their grain size on the WFV have been investigated. The simulation results show that the selection of appropriate gate material and the reduction of metal grain size are the effective solutions to the WFV of TFETs.