Open AccessWire crossing constrained QCA circuit design using bilayer logic decomposition
Author(s) -
Roohi A.,
Thapliyal H.,
DeMara R.F.
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.2622
Subject(s) - computer science , quantum dot cellular automaton , logic gate , electronic circuit , electronic engineering , robustness (evolution) , logic optimization , logic synthesis , cmos , computer engineering , algorithm , engineering , electrical engineering , biochemistry , chemistry , gene
Quantum‐dot cellular automata (QCA) seek potential benefits over CMOS devices such as low‐power consumption, small dimensions, and high‐speed operation. Two prominent QCA concerns of wire crossing complexity and circuit robustness are addressed by developing a three‐step bilayer logic decomposition (BLD) methodology to design QCA‐based logic circuits. The partitioning of QCA computing operations into logic layers realises considerable improvements in complexity, area, and modularity metrics. Moreover, since larger circuits are divided into two increasingly disjoint sub‐planes, verification of the functionality of the design becomes compartmentalised. Design capability of the proposed approach is illustrated and analysed by implementing an area‐efficient full comparator (FC) based on a novel logic realisation. The resulting 1‐bit FC achieves 32% improvement in complexity metrics in comparison with the previous optimal QCA‐based FC. The related waveforms used in verification of the BLD‐generated FC which are obtained by the QCADesigner simulation tool are discussed as a motivating example of the BLD methodology.