Open AccessLow‐power digital latch circuit using magnetic logic device
Author(s) -
Qin Tao,
Cai Li,
Yang Xiaokuo,
Zhang Mingliang
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.2487
Subject(s) - nanomagnet , digital electronics , logic gate , pass transistor logic , electrical engineering , resistor–transistor logic , electronic engineering , computer science , logic family , power (physics) , electronic circuit , engineering , physics , magnetic field , magnetization , quantum mechanics
The in‐plane magnetic logic device is a spin‐based technology which offers several advantages over charged‐based devices such as non‐volatility, ultra‐low power and greater integration density. A novel low‐power digital latch circuit is proposed by using various shaped nanomagnets. Specifically, a pipelined clocking layout is effectively constructed to ensure sequential and reliable operation. The simulation results show that the magnetic logic latch performs well. The proposed circuit is promising in building future ultra‐low power magnetic memories, and may inspire new applications (i.e. magnetic arithmetic circuits).