Open AccessImproving speed of tunnel FETs logic circuits
Author(s) -
Avedillo M.J.,
Núñez J.
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2015.2416
Subject(s) - bootstrapping (finance) , cmos , transistor , electronic circuit , digital electronics , electronic engineering , logic gate , adder , electrical engineering , integrated injection logic , subthreshold conduction , computer science , pass transistor logic , engineering , voltage , mathematics , econometrics
Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. These transistors exhibit asymmetric conduction which can cause sustained noise voltage pulses (bootstrapping) within digital tunnel FET circuits leading to delay degradation. A minor modification of the complementary gate topology to avoid the bootstrapping problem is proposed and its impact on speed at the circuit level is shown. Speed improvements up to 33% have been obtained for 8‐bit ripple carry adders when implemented with the solution.