Open AccessFPGA implementation of a high‐speed, real‐time, windowed standard deviation filter
Author(s) -
Herbert J.,
Wilson S.,
Rakic A.D.,
Taimre T.
Publication year - 2016
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.2407
Subject(s) - field programmable gate array , standard deviation , computer science , computation , signal (programming language) , gate array , filter (signal processing) , algorithm , series (stratigraphy) , representation (politics) , reduction (mathematics) , electronic engineering , computer hardware , mathematics , engineering , statistics , computer vision , law , biology , programming language , geometry , paleontology , politics , political science
Characterisation of the standard deviation of a time‐series signal has uncommon, yet widespread applications. The usual requirement for a representation of signal standard deviation in real‐time implies a high computation speed. A method based on a field programmable gate array (FPGA) implementation is presented. The technique is benchmarked against conventional computational approaches and shows a single windowed standard deviation update calculation of a 16 bit sample can be achieved in 11 ns on a modern CPU. The FPGA implementation is found to be superior to all other approaches examined with an operation time of below 10 ns, and thus provides a useful tool for the real‐time measurement of the standard deviation of signals above 100 MHz.