Open AccessLow‐complexity CRC‐aided early stopping unit for parallel turbo decoder
Author(s) -
Kim Hyeji,
Lee Youngjoo,
Kim JiHoon
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.2262
Subject(s) - critical path method , cyclic redundancy check , galois theory , computer science , parallel computing , gate count , cmos , very large scale integration , computation , multiplier (economics) , arithmetic , computer hardware , mathematics , decoding methods , algorithm , embedded system , electronic engineering , discrete mathematics , engineering , systems engineering , economics , macroeconomics
A low‐complexity distributed cyclic redundancy check (CRC) architecture for the CRC‐aided early stopping unit is proposed. In the previous distributed CRC unit, the general high‐order Galois field (GF) multiplier occupies almost the area of the CRC unit and requires high‐hardware cost and long critical path‐delay. Accordingly, a computation algorithm based on GF arithmetic is analysed and an optimal CRC unit with the small order of the GF multiplier and newly designed linear feedback shift register is proposed. The proposed CRC architecture is implemented in 65 nm CMOS process for radix‐2 2 and radix‐2 4 parallel turbo decoders based on LTE‐Advanced. In the radix‐2 2 system, reductions of about 57.1% of gate count, 31.7% of critical path‐delay and 44.1% of power consumption are achieved compared with the previous work.