Open AccessBuilt‐in parasitic‐diode‐based charge injection technique enhancing data retention of gain cell DRAM
Author(s) -
Chung Yeonbae,
Cheng Weijie,
Das Hritom
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.2237
Subject(s) - data retention , dram , dynamic random access memory , memory cell , optoelectronics , voltage , memory refresh , materials science , node (physics) , diode , electronic engineering , cmos , electrical engineering , computer science , computer hardware , semiconductor memory , transistor , engineering , computer memory , structural engineering
A gain cell embedded dynamic random access memory (eDRAM) with a noble charge injection technique is presented. The gain memory cell is composed of dual‐threshold two logic N‐type MOSs implemented in a generic triple‐well CMOS process. A negative‐voltage toggle on the parasitic junction diode formed between the pocket p‐well and the cell data node couples up the cell storage voltages. It results in a much enhanced retention time in a compact bit area. Moreover, the technique exhibits much strong immunity from the write disturbance. Measured results at 85°C from a 110 nm 64 kbit prototype eDRAM incorporating the proposed technique demonstrate 69% enhanced retention time and 86% smaller write disturbance loss compared with the conventional one.