Open AccessPipelined median architecture
Author(s) -
Cadenas J.
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2015.1898
Subject(s) - pipeline (software) , field programmable gate array , median filter , computer science , filter (signal processing) , noise (video) , reduction (mathematics) , window (computing) , algorithm , parallel computing , computer hardware , mathematics , arithmetic , artificial intelligence , image processing , geometry , image (mathematics) , computer vision , programming language , operating system
The core processing step of the noise reduction median filter technique is to find the median within a window of integers. A four‐step procedure method to compute the running median of the last N W ‐bit stream of integers showing area and time benefits is proposed. The method slices integers into groups of B ‐bit using a pipeline of W / B blocks. From the method, an architecture is developed giving a designer the flexibility to exchange area gains for faster frequency of operation, or vice versa, by adjusting N , W and B parameter values. Gains in area of around 40%, or in frequency of operation of around 20%, are clearly observed by FPGA circuit implementations compared with latest methods in the literature.