Pipelined median architecture

The core processing step of the noise reduction median filter technique is to find the median within a window of integers. A four‐step procedure method to compute the running median of the last N W ‐bit stream of integers showing area and time benefits is proposed. The method slices integers into groups of B ‐bit using a pipeline of W / B blocks. From the method, an architecture is developed giving a designer the flexibility to exchange area gains for faster frequency of operation, or vice versa, by adjusting N , W and B parameter values. Gains in area of around 40%, or in frequency of operation of around 20%, are clearly observed by FPGA circuit implementations compared with latest methods in the literature.