Open AccessFast encoding of quasi‐cyclic low‐density parity‐check codes in IEEE 802.15.3c
Author(s) -
Zhang Peng,
Du Shuai,
Liu Changyin,
Jiang Qianqian
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
ISSN - 1350-911X
DOI - 10.1049/el.2015.1770
Subject(s) - encoder , parity (physics) , computer science , raptor code , parity check matrix , electronic circuit , low density parity check code , encoding (memory) , parity bit , parallel computing , algorithm , decoding methods , arithmetic , mathematics , physics , engineering , electrical engineering , particle physics , error floor , artificial intelligence , operating system
A high‐speed encoder is proposed for quasi‐cyclic low‐density parity‐check codes. By merging some sub‐matrices of a parity‐check matrix H in an approximately lower triangular form, a compact encoding process is obtained, reducing pipeline stages from six to three. Moreover, well‐designed circuits are used to implement back‐substitution and sparse‐matrix–vector multiplication. The low‐density parity‐check (672, 336) code in IEEE 802.15.3c shows that the proposed encoder is easy to implement, runs fast, and requires no memory.