Digital excess loop delay compensation technique with embedded truncator for continuous‐time delta–sigma modulators | Zendy

He Tao | Zendy; Zhang Yi | Zendy; Temes Gabor C. | Zendy

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Digital excess loop delay compensation technique with embedded truncator for continuous‐time delta–sigma modulators

Author(s) -

He Tao,

Zhang Yi,

Temes Gabor C.

Publication year - 2016

Publication title -

electronics letters

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.375

H-Index - 146

eISSN - 1350-911X

pISSN - 0013-5194

DOI - 10.1049/el.2015.1595

Subject(s) - delta sigma modulation , compensation (psychology) , feedback loop , loop (graph theory) , path (computing) , encoder , control theory (sociology) , electronic engineering , computer science , digital to analog converter , sigma , frequency compensation , voltage , electrical engineering , physics , engineering , mathematics , capacitor , cmos , quantum mechanics , psychology , computer security , control (management) , combinatorics , artificial intelligence , psychoanalysis , programming language , operating system

A novel implementation is proposed to relax the specifications of the internal feedback path for a continuous‐time delta–sigma modulator. A truncator is embedded into the digital excess loop delay (ELD) compensation path. Thermometer‐coded truncation is achieved by re‐ordering the reference voltages of the internal quantiser. This requires only a small amount of extra digital circuitry compared to the conventional digital ELD compensation. The digital encoder controlling the digital‐to‐analogue converter is simple, and it only introduces a small ELD.

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