Open AccessDEC‐cache: dynamically electing candidate cache for low power utilising hearing policy
Author(s) -
Joo Hyunwook,
Lee Yong Surk
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.1153
Subject(s) - cache , computer science , smart cache , cache algorithms , cache pollution , cache invalidation , page cache , cache coloring , scheme (mathematics) , cpu cache , embedded system , parallel computing , mathematical analysis , mathematics
On‐chip cache memory is one of the largest power consumers in modern microprocessors. A dynamic way prediction scheme utilising a hearing policy is proposed for a low‐power level‐one cache design that handles power limit issues. The high prediction accuracy of the dynamically electing candidate (DEC)‐cache helps to prevent large miss penalties. Owing to the high prediction accuracy, the experimental results show that the DEC‐cache structure improves the energy‐delay product by 26% compared with the existing buffered dual‐mode cache.