Open AccessControlled delay‐through dynamic logic: leakage‐tolerant high‐speed dynamic logic
Author(s) -
Dev A.,
Sharma R.K
Publication year - 2015
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el.2015.0952
Subject(s) - dynamic logic (digital electronics) , domino logic , computer science , asynchronous circuit , logic level , sequential logic , pass transistor logic , dynamic demand , electronic engineering , propagation delay , logic gate , control logic , clock skew , electronic circuit , clock gating , block (permutation group theory) , leakage (economics) , power–delay product , logic family , clock signal , logic synthesis , power (physics) , synchronous circuit , electrical engineering , engineering , transistor , cmos , algorithm , voltage , mathematics , digital electronics , adder , quantum mechanics , physics , macroeconomics , geometry , economics
A new model for dynamic logic is proposed with low power consumption and leakage without the degradation of speed. This logic works perfectly with cascaded and differential style without inverters. Controlled delay‐through dynamic logic (CDTDL) is comparatively faster than other dynamic logics because of the parallel‐type configuration with clock and inputs. CDTDL‐based circuits can perform better in high‐frequency operations due to lower propagation delay and dynamic power consumption at the cost of area. The proposed technique can avoid the chance of leakage current with the help of a control block and a delayed clock mechanism. The simulation results show that the new dynamic logic using 180 nm technology yields a minimum 49.7% improvement in power delay product compared with its predecessors such as conventional domino and current comparison‐based domino for standard circuits.